Regarding a Si (silicon) MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which is a power semiconductor device used widely, a main determination factor for breakdown voltage is the upper limit of an electric field strength with which a drift layer serving as a breakdown voltage holding region can withstand. A drift layer made of Si can be broken at a portion fed with an electric field of about 0.3 MV/cm or more. Accordingly, it is required to suppress the electric field strength to be less than a predetermined value in the entire breakdown voltage holding region of the MOSFET. The simplest method is to provide the breakdown voltage holding region with a low impurity concentration. However, this method provides a large on-resistance of the MOSFET, disadvantageously. In other words, there is a trade-off relation between the on-resistance and the breakdown voltage.
Regarding a typical Si MOSFET, Japanese Patent Laying-Open No. 9-191109 illustrates a trade-off relation between the on-resistance and the breakdown voltage in consideration of a theoretical limit resulting from a property value of Si. In order to cancel this trade off, it is disclosed to add a lower p type embedded layer and an upper p type embedded layer in an n base layer provided on an n type substrate provided on a drain electrode. By the lower p type embedded layer and the upper embedded layer, the n base layer is divided into a lower stage, a middle stage, and an upper stage, each of which has an equal thickness. According to this publication, voltage is equally held by each of the three stages, whereby the maximum electric field of each stage is maintained to be equal to or less than the critical electric field strength.